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cy22381 CY223811 three-pll general purpose flash programmable clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07012 rev. *i revised may 17, 2011 features three integrated phase-locked loops ultra-wide divide counters (eight -bit q, eleven-bit p, and seven-bit post divide) improved linear crystal load capacitors flash programmability field programmability low-jitter, high-accuracy outputs power-management options (shutdown, oe, suspend) configurable crystal drive strength frequency select option through external lvttl input 3.3 v operation 8-pin small outline integrated circuit (soic) package (cy22381) 8-pin soic package with nipdau lead finish (CY223811) cyclocks rt? support functional description the cy22381 is the next-generation programmable flash programmable clock for use in networking, telecommunication, datacom, and other general-purpose applications. the cy22381 offers up to three configurable outputs in a 8-pin soic, running off a 3.3 v power supply. the on-chip reference oscillator is designed to run off an 8?30-mhz crystal, or a 1?166-mhz external clock signal. the cy22381 has a three plls driving 3 programmable output clocks. the output clocks are derived from the pll or the reference frequency (ref). output post dividers are available for either. the CY223811 is the cy22381 with nipdau lead finish. xtalin xtalout fs/suspend shutdown /oe configuration flash osc. pll1 11-bit p 8-bit q pll2 11-bit p 8-bit q pll3 11-bit p 8-bit q 4 3 switch crosspoint divider 7-bit divider 7-bit divider 7-bit clka clkb clkc logic block diagram [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 2 of 11 contents features ............................................................................. 1 functional description ..................................................... 1 logic block diagram ........................................................ 1 pinouts .............................................................................. 3 pin definitions .................................................................. 3 operation ........................................................................... 3 configurable plls ....................................................... 3 general-purpose input ........... ..................................... 3 crystal input .......... .............. .............. .............. ............ 3 crystal drive level and power .................................... 4 output configuration ................................................... 4 power-saving features ............................................... 4 improving jitter ............................................................ 4 cyclocks rt software ..................................................... 4 maximum ratings ............................................................. 5 operating conditions ....................................................... 5 recommended crystal specifications ........................... 5 electrical characteristics ................................................. 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 6 possible configurations ............................................... 8 ordering information ........................................................ 8 package drawing and dimensions ................................ 9 acronyms .......................................................................... 9 document conventions ................................................... 9 units of measure ......................................................... 9 document history page ................................................. 10 sales, solutions, and legal information ...................... 11 worldwide sales and design s upport ......... .............. 11 products .................................................................... 11 psoc solutions ......................................................... 11 [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 3 of 11 pinouts figure 1. cy22381, CY223811- 8-pin soic operation the cy22381 is an upgrade to the existing cy2081. the new device has a wider frequency range , greater flexibility, improved performance, and incorporates m any features that reduce pll sensitivity to external system issues. the device has three plls that allow each output to operate at an independent frequencies. these three plls are completely programmable. the CY223811 is the cy22381 with nipdau lead finish. configurable plls pll1 generates a frequency that is equal to the reference divided by an eight-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll1 is sent to the crosspoint switch. the frequency of pll1 can optionally be changed by using the exter nal cmos general purpose input. see the following section on ?g eneral-purpose input? for more detail. pll2 generates a frequency that is equal to the reference divided by an eight-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll2 is sent to the crosspoint switch. pll3 generates a frequency that is equal to the reference divided by an eight-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll3 is sent to the cross-point switch. general-purpose input the cy22381 features an output c ontrol pin (pin 8) that can be programmed to control one of four features. when programmed as a frequen cy select (fs), the input can select between two arbitrarily programmed frequency settings. the frequency select can change the following; the frequency of pll1, the output divider of clkb, and the output divider of clka. any divider change as a result of switching the fs input is guaranteed to be glitch free. the general-purpose input can simultaneously control the suspend feature, turning off a set of plls and outputs determined during programming. when programmed as an output enable (oe) the input forces all outputs to be placed in a three-state condition when low. when programmed as a shutdown, the input forces a full chip shutdown mode when low. crystal input the input crystal oscillator is an important feature of this device because of its flexibility and performance features. the oscillator inverter has prog rammable drive strength. this allows for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. the input load capacitors are placed on-die to reduce external component cost. these capacitors are true parallel-plate capacitors for ultra-linear perf ormance. these were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. non-linear (fet gate) crystal load capacitors must not be used for mpeg, communications, or other applications that are sensitive to absolute frequency requirements the value of the load capacitors is determined by six bits in a programmable register. the load capacitance can be set with a resolution of 0.375pf for a total crystal load range of 6pf to 30pf. for driven clock inputs the input load capacitors may be completely bypassed. this enables the clock chip to accept driven frequency inputs up to 166 mhz. if the application requires a driven input, then xtalout must be left floating. pin definitions name pin number description clkc 1 configurable clock output c gnd 2 ground xtalin 3 reference crystal input or external reference clock input xtalout 4 reference crystal feedback (float if xtalin is driven by external reference clock) clkb 5 configurable clock output b clka 6 configurable clock output a v dd 7 power supply fs/suspend / oe/shutdown 8 general purpose input. can be frequency contro l, suspend mode control, output enable, or full-chip shutdown. 1 2 3 4 5 6 7 8 clkc gnd xtalin xtalout fs/ suspend /oe/ shutdown v dd clka clkb [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 4 of 11 crystal drive level and power crystals are specified to a ccept a maximum drive level. generally, larger crystals can accept more power. the drive level specification in the table below is a general upper bound for the power driven by the oscillator circuit in the cy22381. for a given voltage swing, power dissipation in the crystal is proportional to esr and proportional to the square of the crystal frequency. (note that actual esr is sometimes much less than the value specified by the cryst al manufacturer.) power is also almost proportional to the square of c l . power can be reduced to less than the dl specification in the table below by selecting a reduced frequency crystal with low c l and low r 1 (esr). output configuration under normal operation there are four internal frequency sources that may be routed through a programmable crosspoint switch to any of the three outputs through programmable seven-bit output dividers. the four sources are: reference, pll1, pll2, and pll3. the following is a description of each output. clka?s output originates from the crosspoint switch and goes through a programmable seven-bit post divider. the seven-bit post divider derives its value from one of two programmable registers controlled by fs. clkb?s output originates from the crosspoint switch and goes through a programmable seven-bit post divider. the seven-bit post divider derives its value from one of two programmable registers controlled by fs. clkc?s output originates from the crosspoint switch and goes through a programmable seven-bit post divider. the seven-bit post divider derives its value from one programmable register. the clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15pf. while driving multiple loads is possible with the proper termination, it is generally not recommended. power-saving features when configured as oe, the general-purpose input three-states all outputs when pulled low. when configured as shutdown, a low on this pin three-states all outputs and shuts off the plls, counters, the reference oscillator, and all other active components. the resulting current on the v dd pins is less than 5 ? a (typical). after leaving sh utdown mode, the plls has to relock. when configured as suspend , the general-purpose input can be configured to shut down a customizable set of outputs and/or plls, when low. all plls and any of the outputs can be shut off in nearly any combination. the only limitation is that if a pll is shut off, all outputs derived from it must also be shut off. suspending a pll shuts off all associated logic, while suspending an output forces a three-state condition. improving jitter jitter optimization control is usef ul in mitigating problems related to similar clocks switching at the same moment and causing excess jitter. if one pll is driving more than one output, the negative phase of the pll can be selected for one of the outputs. this prevents the output edges from aligning, allowing superior jitter performance. cyclocks rt software cyclocks rt is our second-gener ation application that allows users to configure this device. the easy-to-use interface offers complete control of the many feat ures of this family including input frequency, pll and output frequencies, and different functional options. data sheet frequency range limitations are checked and performance tuning is automatically applied. you can download a free copy of cyclocks rt on cypress?s web site at http://www.cypress.com . [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 5 of 11 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. supply voltage ..............................................?0.5 v to +7.0 v dc input voltage .............................?0.5 v to + (v dd + 0.5 v) storage temperature.................. ................... ?65 c +125 c junction temperature.................................................. 125 c data retention at tj = 125 c.................................> 10 years maximumrprogamming cycles....... .............. .............. .......100 package power dissipation....................................... 250 mw static discharge voltage (per mil-std-883, method 301 5) ............ ........ ....... ? 2000v latch up (per jedec 17) .................................... ? 2 0 0 m a operating conditions parameter description min typ max unit v dd supply voltage 3.135 3.3 3.465 v t a commercial operating temperature, ambient 0 ? +70 c industrial operating temperature, ambient ?40 ? +85 c c load_out max. load capacitance ? ? 15 pf f ref external reference crystal 8 ? 30 mhz external reference clock [2] , ccommercial 1?166mhz external reference clock [2] , industrial 1?150mhz t pu power up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms recommended crystal specifications parameter description description min typ. max unit f nom nominal crystal frequency parallel resonance, fundamental mode 8 ? 30 mhz c lnom nominal load capacitance 8 ? 20 pf r 1 equivalent series resistance (esr) fundamental mode ? ? 50 ? dl crystal drive level no external series resistor assumed ? 0.5 2 mw notes 1. unless otherwise noted, electrical and switching characte ristics are guaranteed across these operating conditions. 2. external input reference clock must have a du ty cycle between 40% and 60%, measured at v dd /2. 3. guaranteed by design, not 100% tested. electrical characteristics parameter description conditions [1] min typ max unit i oh output high current [3] v oh = v dd ? 0.5, v dd = 3.3 v 12 24 ? ma i ol output low current [3] v ol = 0.5 v, v dd = 3.3 v 12 24 ? ma c xtal_min crystal load capacitance [3] capload at minimum setting ? 6 ? pf c xtal_max crystal load capacitance [3] capload at maximum setting ? 30 ? pf c in input pin capacitance [3] except crystal pins ? 7 ? pf v ih high-level input voltage cmos levels,% of v dd 70% ? ? v dd v il low-level input voltage cmos levels,% of v dd ??30%v dd i ih input high current v in = v dd ? 0.3 v ? <1 10 ? a i il input low current v in = +0.3 v ? <1 10 ? a i oz output leakage current three-state outputs ? ? 10 ? a [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 6 of 11 i dd total power supply current 3.3 v power supply; 3 outputs at 50 mhz ? 35 ? ma 3.3 v power supply; 3 outputs at 166 mhz ? 70 ? ma i dds total power supply current in shutdown mode shutdown active ? 5 20 ? a switching characteristics parameter name description min typ. max unit 1/t 1 output frequency [3, 5] clock output limit,commercial ? ? 200 mhz clock output limit, industrial ? ? 166 mhz t 2 output duty cycle [3, 6] duty cycle for output s, defined as t 2 ? t 1 , fout < 100 mhz, divider >= 2, measured at v dd /2 45% 50% 55% duty cycle for output s, defined as t 2 ? t 1 , fout > 100 mhz or divider = 1, measured at v dd /2 40% 50% 60% t 3 rising edge slew rate [3] output clock rise time, 20% to 80% of v dd 0.75 1.4 ? v/ns t 4 falling edge slew rate [3] output clock fall time, 20% to 80% of v dd 0.75 1.4 ? v/ns t 5 output three-state timing [3] time for output to enter or leave three-state mode after shutdown /oe switches ? 150 300 ns t 6 clock jitter [3, 7] peak-to-peak period jitter, clk outputs measured at v dd /2 ?200 ? ps t 7 lock time [3] pll lock time from power up ? 1.0 3 ms switching waveforms electrical characteristics parameter description conditions [1] min typ max unit notes 4. guaranteed by design, not 100% tested. 5. guaranteed to meet 20% ? 80% output thresholds and duty cycle specifications. 6. reference output duty cycle depends on xtalin duty cycle. 7. jitter varies significantly with configuration. refer ence output jitter depends on xtalin jitter and edge rate. t 1 output t 2 t 3 t 4 figure 2. all outputs, duty cycle and rise and fall time t 5 oe all outputs t 5 three-state figure 3. output three-state timing [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 7 of 11 test circuit switching waveforms (continued) clk output t 6 figure 4. clk output jitter select old select new select stable f old f new t 7 output figure 5. frequency change 0.1 mf v dd clkout c load gnd outputs [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 8 of 11 some product offerings are factory progra mmed customer specific devi ces with customized part numbe rs. the possible configura tions table shows the available device types, but not complete pa rt numbers. contact your local cypress fae or sales representa tive for more information. possible configurations ordering code definitions ordering information ordering code package type operating range operating voltage pb-free CY223811fxi 8-soic with nipdau lead frame industrial (t a =?40 c to 85 c) 3.3 v cy22381fxc [10] 8-soic commercial (t a =0 c to 70 c) 3.3 v cy22381fxct 8-soic ? tape and reel commercial (t a =0 c to 70 c) 3.3 v cy22381fxi 8-soic industrial (t a =?40 c to 85 c) 3.3 v cy22381fxit 8-soic ? tape and reel industrial (t a =?40 c to 85 c) 3.3 v programmer cy3672-usb programmer cy3699 cy22381f adapter for cy3672-usb ordering code package type operating range operating voltage cy22381si-xxxt [8, 9] 8-soic ? tape and reel industrial (t a =?40c to 85c) 3.3 v pb-free cy22381sxc-xxx [8] 8-soic commercial (t a =0 c to 70 c) 3.3 v cy22381sxc-xxxt [8] 8-soic ? tape and reel commercial (t a =0 c to 70 c) 3.3 v cy22381sxi-xxx [8] 8-soic industrial (t a =?40 c to 85 c) 3.3 v cy22381sxi-xxxt [8] 8-soic ? tape and reel industrial (t a =?40 c to 85 c) 3.3 v notes 8. the cy22381si-xxx, cy22381sxc-xxx and cy22381sxi-xxx are factor y programmed configurations. fa ctory programming is available for high-volume design opportunities of 100ku/year or more in production. for more det ails, contact your local cypress fae or cypress sales representa tive. 9. not recommended for new designs. 10. the cy22381fszc and cy22381fxc are ident ical. for new designs, use cy22381fxc. t = tape and reel, blank = tube configuration specific ident ifier (factory programmed) temperature range: c = co mmercial, i = industrial package: s = soic, leaded sx = soic, pb-free x = soic, pb-free f = field programmable, blank = factory programmed lead finish:1 = nipdau, blank = unspecified part identifier company code: cy = cypress semiconductor 22381 cy sx c (-xxx) (1) (f) (t) [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 9 of 11 package drawing and dimensions acronyms document conventions units of measure 51-85066-*d figure 6. 8-pin (150-mil) soic acronym description cmos complementary metal oxide semiconductor esr equivalent series resistance fet field effect transistor mpeg motion picture experts group oe output enable pll phase-locked loop soic small outline integrated circuit symbol unit of measure ? c degree celcius a micro amperes ma milli amperes ms milli seconds mw milli watts mhz mega hertz ? amicro amps ? f micro farads ns nano seconds pf pico farad ps pico seconds vvolts [+] feedback
cy22381 CY223811 document #: 38-07012 rev. *i page 10 of 11 document history page document title: cy22381, CY223811 three-pll general purpose flash programmable clock generator document number: 38-07012 revision ecn orig. of change submission date description of change ** 106737 tlg 07/03/01 new data sheet *a 108514 jwk 08/23/01 updated based on characterization results. removed ?preliminary? heading removed soldering temperature rating. split crystal load into two typical specs representing digital settings range. changed t 5 max to 300 ns changed t 6 typical to 200 ps. changed t 7 typical to 1.0 ms *b 110053 ckn 12/10/01 changed from preliminary to final *c 121863 rbi 12/14/02 added power up requirements to operating conditions information *d 279431 rgl see ecn added lead-free devices *e 2584052 aesa 10/10/08 updated template. added note 8 and 9. added part number cy22381fc, cy22381fct, cy3672-usb, cy3699, cy22381fszc in ordering information table. removed part number cy 22381fi, cy 22381fit, cy22381sc-xxx, cy22381sc-xxxt, cy22381si-xxx, a nd cy22381si-xxxt in ordering information table. added CY223811fxi (nipdau lead finish). changed lead-free to pb-free. *f 2620588 kvm/aesa 12/11/08 add cy 223811 to the document title distinguish between cy22381 and CY223811 in page 1 features section add part number cy22381si-xxxt in ordering info rmation table. *g 2897317 kvm 03/22/10 removed obsolete parts from or dering information table and moved ?xx? parts to possible configurations table updated package diagram *h 3065190 kvm/bash 01/17/11 add crystal parameter table, or dering code definition, acronym and units tables. crystal drive level and power. remove ftg from cy3672. removed benefits section and replaced with functional description section. *i 3259420 bash 05/17/2011 updated as per template [+] feedback
document #: 38-07012 rev. *i revised may 17, 2011 page 11 of 11 all products and company names mentioned in this document may be the trademarks of their respective holders. cy22381 CY223811 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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